A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis

Static transistor level timing analysis has become more and more accepted method for performance evaluation because of its reduced design cycle time when compared to the vector based timing analysis. These static timing analysis tools use transistor level delay modelling to identify timing-critical paths and estimate performance of the design. With increase in complexity of designs it becomes necessary to verify the timing-critical paths using spice-simulations. In order to perform accurate modelling for spice simulations, it becomes imperative to identify all the devices and the signal-states on the nodes, for a given input to output transition. The current techniques use greedy approaches for each input to output transition in a channel connected component. These techniques consider turningon all transistors on the primary conducting path and turning-off remaining transistors on the side-paths. Thus, these techniques don’t consider appropriate loading on the output node due to transistors on the side-paths and the fanout paths. These techniques also don’t consider the input signal correlations. This paper presents a three-tier heuristics to determine side path assertions, such that it maximizes, as much as possible, the load at the output node, for a given set of input to output transition. Also, a method to perform the fanout path assertions is presented. This technique has been used for spice-verification of the timing-critical paths of transistor level designs. The results have been compared using spice simulations of the same designs.